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1/16 www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. high reliability seri es serial eeproms wl-csp eeprom family i 2 c bus bu9897gul-w description bu9897gul-w is a serial eeprom of i 2 c bus interface method. memory density is 128kbit (16,384 8bit) , compact package vcsp50l2. features 1) completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock (scl) and serial data (sda) 2) other devices than eeprom can be connected to the same port, saving microcontroller port. 3) 1.7 ~ 5.5v single power source action most suitable for battery use. 4) fast mode 400khz at 1.7 ~ 5.5v 5) page write mode useful for initial value write at factory shipment. 6) auto erase and auto end function at data rewrite. 7) low current consumption at write operation (5.0v) : 0.5ma (typ.) at read operation (5.0v) : 0.2ma (typ.) at standby operation (5.0v) : 0.1a (typ.) 8) write mistake prevention function write (write protect) function added write mistake prevention function at low voltage 9) data rewrite up to 1,000,000 times 10) data kept for 40 years 11) noise filter built in scl / sda terminal 12) shipment data all address ffh page write product number number of pages bu9897gul-w 64byte absolute maximum ratings (ta=25 ) parameter symbol ratings unit impressed voltage v cc -0.3 ~ 6.5 v permissible dissipation pd 220 *1 mw storage temperature range tstg -65 ~ 125 action temperature range topr -40 ~ 85 terminal voltage -0.3 ~ v cc +1.0 *2 v *1 when using at ta=25 or higher, 2.2mw to be reduced per 1 *2 the max value of terminal voltage is not over 6.5v. recommended operating conditions parameter symbol ratings unit power source voltage v cc 1.7 ~ 5.5 v input voltage v in 0 ~ v cc no.10001eat24
technical note 2/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. memory cell characteristics (ta=25 , vcc=1.7~5.5v) parameter limits unit min. typ. max. number of data rewrite times *1 1,000,000 times data hold years *1 40 years *1 not 100% tested electrical characteristics (unless otherwise specified ta=-40~85 , v cc =1.7~5.5v) parameter symbol limits unit condition min typ. max. "h" input voltage1 v ih1 0.7v cc v cc +1.0 v "l" input voltage1 v il1 0.3 0.3vcc v "l" output voltage1 v ol1 0.4 v i ol =3.0ma, 2.5v Q v cc Q 5.5v(sda) "l" output voltage2 v ol2 0.2 v i ol =0.7ma, 1.7v Q v cc 2.5v(sda) input leakage current i li 1 1 a v in =0v ~ v cc output leakage current i lo 1 1 a v out =0v ~ v cc (sda) current consumption at action i cc1 2.5 ma v cc =5.5v , f scl =400khz, twr=5ms byte write, page write i cc2 0.5 ma v cc =5.5v , f scl =400khz random read, current read, sequential read standby current i sb 2.0 a v cc =5.5v , sda ? scl=v cc , wp=gnd this product is not designed for protection against radioactive rays. action timing characteristics (unless otherwise specified ta=-40 ~ 85 ? v cc =1.7 ~ 5.5v) parameter symbol limits unit min. typ. max. scl frequency fscl 400 khz data clock "high" time thigh 0.6 s data clock "low" time tlow 1.2 s sda, scl rise time *1 tr 0.3 s sda, scl fall time *1 tf 0.3 s start condition hold time thd:sta 0.6 s start condition setup time tsu:sta 0.6 s input data hold time thd:dat 0 ns input data setup time tsu:dat 100 ns output data delay time tpd 0.1 0.9 s output data hold time tdh 0.1 s stop condition data setup time tsu:sto 0.6 s bus release time before transfer start tbuf 1.2 s internal write cycle time twr 5 ms noise removal valid period (sda,scl terminal) ti 0.1 s wp hold time thd:wp 0 ns wp setup time tsu:wp 0.1 s wp valid time thigh:wp 1.0 s *1 : not 100% tested
technical note 3/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. sd a scl d0 ack stop condition start condition t wr write data(n) sync data input/output timing block diagram fig.2 block diagram thigh:wp wp sda d1 d0 a ck a ck data(1) data(n) scl twr sda sda thd :sta thd :dat tsu :dat tbuf tpd tdh tlow thigh tr tf scl (input) (output) input read at the rise edge of scl data output in sync with the fall of scl fig.1-(a) sync data input / output timing fig.1-(b) start - stop bit timing fig.1-(c) write cycle timing fig.1-(d) wp timing at write execution fig.1-(e) wp timing at write cancel at write execution, in the area from the d0 taken clock rise of the first data(1), to twr, set wp= 'low'. by setting wp "high" in the area, write can be cancelled. when it is set wp = 'high' during twr, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. scl sd a wp thd wp stop condition twr d1 d0 a ck a ck data(1) data(n) tsu wp sda tsu :sta tsu :sto thd :sta start bit stop bit scl 8 7 6 5 4 3 2 1 sda scl wp vcc gnd a2 a1 a0 adddress decoder slave - word address register data re g ister control circuit high voltage generating circuit power source volta g e detection 14bit 8bit ack start stop 128kbit eeprom array 14bit
technical note 4/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. pin assignment and description characteristic data (the following values are typ. ones.) land no. terminal name input / output function c4 gnd - please set this open. please don?t connect this gnd. c3 a1 input slave address c2 a2 input slave address c1 gnd - reference voltage of all input / output b4 gnd - please set this open. please don?t connect this gnd. b3 a0 input slave address b1 sda input / output slave and word addre ss, serial data input serial data output a4 gnd - please set this open. please don?t connect this gnd. a3 vcc - power supply a2 wp input write protect terminal a1 scl input serial clock input 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supplyvoltage : vcc(v) input leak current : i li (ua) spec ta=-40 ta=25 ta=85 0 0.2 0.4 0.6 0.8 1 0123456 l output current : i ol (ma) l output voltage : v ol (v) spec ta=-40 ta=25 ta=85 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage : vcc(v) output leak current : i lo (ua) spec ta=-40 ta=25 ta=85 0 1 2 3 4 5 6 0123456 supply voltage : vcc(v) h input voltage : v ih (v) ta=-40 ta=25 ta=85 spec 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678 l output current : i ol (ma) l output voltage : v ol (v) spec ta=-40 ta=25 ta=85 fig.6 'l' output voltage v ol -i ol (vcc=1.7v) 0 1 2 3 4 5 6 0123456 supply voltage : vcc(v) l input voltage : v il (v) ta=-40 ta=25 ta=85 fig.7 'l' output voltage v ol -i ol (vcc=2.5v) fig.8 input leak current i li (a0,a1,a2,scl,wp) fig.9 output leak current i lo (sda) spec fig.4 'h' input voltage v ih (a0,a1,a2,scl,sda,wp) fig.5 'l' input voltage v il (a0,a1,a2,scl,sda,wp) fig.3 bu9897gul-w(bottom view) vss sda a2 a1 a0 scl wp vcc vss vss vss c b a 1 2 34
technical note 5/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) -200 -100 0 100 200 300 0123456 supply voltage : vcc(v) input data set up time : t su : dat (ns) ta=-40 ta=25 ta=85 spec 0 1 2 3 4 0123456 supply voltage : vcc(v) output data delay time : t pd (us) spec ta=-40 ta=25 ta=85 0 0.5 1 1.5 2 2.5 0123456 supply voltage : vcc(v) stanby current : i sb (ua) spec ta=-40 ta=25 ta=85 -0.1 0.9 1.9 2.9 3.9 4.9 5.9 0123456 supply voltage : vcc(v) start condition set up time : tsu:sta(ua) ta=-40 ta=25 ta=85 spec 0.1 1 10 100 1000 10000 0123456 supply voltage : vcc(v) scl frequency : f?hz spec ta=-40 ta=25 ta=85 -200 -150 -100 -50 0 50 0123456 supply voltage : vcc(v) input data hold time : t hd: sta (ns) spec ta=-40 ta=25 ta=85 0 0.5 1 1.5 2 2.5 0123456 supply voltage : vcc(v) current consumption at writing : icc1(ma) spec ta=-40 ta=25 ta=85 fig.12 stanby operation i sb 0 1 2 3 4 5 0123456 supply voltage : vccv clk l time : t low (us) spec ta=-40 ta=25 ta=85 fig.15 data clock low period t low 0 1 2 3 4 5 0123456 supply voltage : vcc(v) start condition hold time : t hd : sta (us) spec ta=-40 ta=25 ta=85 fig.16 start condition hold time t hd : sta fig.17 start condition setup time t su : sta fig.18 input data hold time t hd : dat high fig.19 input data hold time hd : dat (low fig.20 input data setup time su: dat (high) fig.21 input data setup time t su : dat (low) 0 1 2 3 4 0123456 supply voltage : vcc(v) output data delay time : t pd (us) spec ta=-40 ta=25 ta=85 fig.22 ' l ' data output delay time t pd 0 fig.23 'h' data output delay time pd 1 -200 -150 -100 -50 0 50 0123456 supply voltage : vcc(v) input data hold time : t hd :dat (ns) ta=-40 ta=25 ta=85 spec -200 -100 0 100 200 300 0123456 supply voltage : vcc(v) input data set up time : t su: dat (ns) ta=-40 ta=25 ta=85 spec 0 1 2 3 4 5 0123456 supply voltage : vcc(v) bus open time before transmission : t buf (us) spec ta=-40 ta=25 ta=85 fig.24 bus open time before transmission buf fig.13 scl frequency f scl 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) current consumption at reading : icc2(ma) ta=-40 ta=25 ta=85 spec fig.11 current consumption at read operation i cc 2 (fscl=400khz) 0 1 2 3 4 5 0123456 supply voltage : vcc(v) data clk h time : t high (ua) spec ta=-40 ta=25 ta=85 fig.14 data clock high period t high fig.10 current consumption at write operation i cc 1 (fscl=400khz) 0 0.5 1 1.5 2 2.5 3 3.5 0123456 supply voltage : vcc(v) current consumption at writing : icc1(ma) spec ta=-40 ta=25 ta=85
technical note 6/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) 0 1 2 3 4 5 6 0123456 supply voltage : vcc(v) internal writing cycle time : t wr (ms) spec ta=-40 ta=25 ta=85 fig.25 internal writing cycle time wr 0 0.2 0.4 0.6 0.8 1 0123456 supply voltage : vcc(v) noise reduction efective time : t l (scl h) (us) spec ta=-40 ta=25 ta=85 fig.26 noise reduction efection time t l scl h 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 supply volatge : vcc(v) noise reduction efective time : t l (sda h)(us) ta=-40 ta=25 ta=85 spec 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) noise reduction effective time : t l (sad l)(us) spec ta=-40 ta=25 ta=85 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0123456 supply voltage : vcc(v) wp set up time : t su : wp (us) spec ta=-40 ta=25 ta=85 fig.31 wp efective time t high : wp 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supplyvoltage : vcc(v) wp effective time : t high : wp (us) spec ta=-40 ta=25 ta=85 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) noise reduction efective time : t l (scl l)(us) spec ta=-40 ta=25 ta=85 fig.27 noise reduction efective time t l scl l fig.28 noise resuction efecctive time sda h fig.29 noise reduction efective time t l sda l fig.30 wp setup time t su : wp
technical note 7/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and ends by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices c onnected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are ?master? that generates clock and control communication start and end, and ?slave? that is controlled by addresses peculiar to devices. eeprom becomes ?slave?. and the devic e that outputs data to bus during data communication is ca lled ?transmitter?, and the device that receives data is called ?receiver?. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start condi tion (start bit) or not, therefore, unless this condition is satisfied, any command is executed. stop condition (stop bit recognition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device (-com at slave address inpu t of write command, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address input of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write action outputs acknowledge signal) (ack signal) 'low', at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detects acknowledge signal (ack signal) 'low'. when acknowledge signal (ack signal) is detected, and stop condition is not sent from the mast er (-com) side, this ic continues data output. when acknowledge signal (ack signa l) is not detected, this ic stops data transfer, and recognizes stop condition (stop bit), and ends read action. and this ic gets in standby status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? the most insignificant bit ( w / r --- write / read ) of slave address is used for designating write or read action, and is as shown below. setting w / r to 0 --- write (setting 0 to word address setting of random read) setting w / r to 1 --- read type slave address bu9897gul-w 1 0 1 0 0 0 0 w / r fig.32 data transfer timing 89 89 89 s p condition condition a ck stop a c k data data a ddress start r/w a ck 1-7 sda scl 1-7 1-7
technical note 8/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. write command write cycle ? arbitrary data is written to eeprom. when to write only 1 by te, byte write normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. the maximum number of write bytes is specified per device of each capacity.up to 64 arbitrary bytes can be written. ? data is written to the address designated by word address (n-th address). ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk: up to 64 bytes. (refer to "internal address increment of "notes on page write cycle" in p9/16.) ? as for page write cycle of bu9897gul-w , after the signific ant 7 bits of word address, are designated arbitrarily, by continuing data input of 2 bytes or more , the address of insignificant 6 bits is incremented internally, and data up to 64 bytes can be written. 0 0 1 1 0 0 w r i t e s t a r t r / w s t o p 1st word address data slave address 0 d0 a c k sda line a c k a c k wa 13 wa 0 a c k 2nd word address d7 fig.33 byte write cycle fig.34 page write cycle w r i t e s t a r t r / w a c k s t o p 1st word address(n) sda line a c k a c k data(n+31) a c k slave address 1 0 0 10 d0 data(n) d0 d7 a c k 2nd word address(n) wa 0 wa 13 0 0
technical note 9/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. notes on write cycle continuous input notes on page write cycle internal address increment list of numbers of page write product number number of pages bu9897gul-w 64byte the above numbers are maximum bytes for respective types. any bytes below these can be written. in the case of bu9897gul-w, 1 page = 64bytes, but the page write cycle write time is 5ms at maximum for 64byte bulk write. it does not stand 5ms at maximum 64byte = 320ms(max.). write protect (wp) terminal ? write protect (wp) function when wp terminal is set vcc (h level), data rewrite of all addre ss is prohibited. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this te rminal to vcc or gnd, or control it to h level or l level. do not use it open. at extremely low voltage at power on/of f, by setting the wp terminal 'h', mistake write can be prevented. during twr, set the wp terminal always to 'l '. if it is set 'h', writ e is forcibly terminated. fig.35 page write cycle for example, when it is st arted from address 1eh, therefore, increment is made as below, 1eh 1fh 00h 01h ??? * 1eh ??? 16 in hexadecimal, therefore, 00011110 becomes a binary number. w r i t e s t a r t r / w a c k s t o p word address(n) data(n) sda line a c k data(n+31) a c k slave address 10 0 1 a0 a1 a2 wa 7 d0 d7 d0 a c k wa 0 1 1 00 next command twr(maximum 5ms) command is not accepted for this period. at stop (stop bit) write starts. wa12 ----- wa5 wa4 wa3 wa2 wa1 wa0 0 ----- 0 0 0 0 0 0 0 ----- 0 0 0 0 0 1 0 ----- 0 0 0 0 1 0 0 ----- 0 1 1 1 0 1 0 ----- 0 1 1 1 1 0 0 ----- 0 0 0 0 0 0 --------- --------- significant bit is fixed. no digit up 1eh iincrement page write mode
technical note 10/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal addr ess register without designating address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is available, and the next address data can be read in succession. ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, and stop condition is not sent from master (-com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ack signal after d0 and sda signal is started at scl signal 'h'. ? when 'h' is not input to ack signal after d0, seque ntial read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycle, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition where 'h' is input to ack signal after arbitrary d0 and sda is started at scl signal 'h'. fig.36 random read cycle fig.37 current read cycle fig.38 sequential read cycle (in the case of current read cycle) it is necessary to input 'h' to the last ack. it is necessary to input 'h' to the last ack. s t a r t s t o p sd a line a c k data(n) a c k slave address 10 0 1 0 d0 d7 r / w r e a d 0 0 w r i t e s t a r t r / w a c k s t o p 1st word address(n) sda line a c k a c k data(n) a c k slave address 1 0 0 1 0 0 0 d7 d0 2nd word address(n) a c k s t a r t slave address 1 0 0 1 a2 a1 r / w r e a d a0 wa 0 w a 13 r e a d s t a r t r / w a c k s t o p data ( n ) sda line a c k a c k data ( n+x ) a c k slave address 10 0 1 0 d0 d7 d0 d7 0 0
technical note 11/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. software reset software reset is executed when to avoid malfunction after po wer on, and to reset during command input. software reset has several kinds, and 3 kids of them are shown in the figure below. (refer to fig.39(a), fi g.39(b), fig.39(c).) in dummy clock input area, release the sda bus ('h' by pull up). in du mmy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefore, if 'h' is input forcib ly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write, all input commands are ignored, theref ore ack is not sent back. during internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ack signal sends back 'l', then it means end of write action, while if it s ends back 'h', it means now in writing. by use of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, w / r = 0, when to carry out current read cycle after write, slave address w / r = 1 is sent, and if ack signal sends back 'l', then execut e word address input and data so forth. slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack=low is sent back, so input next word address and data in succession. t wr t wr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l fig.40 case to continuously write by acknowledge polling scl 2 1 8 9 dummy clock9 start fig.39-(b) the case of start+9 dummy clock + start + command input start normal command normal command sda 1 2 13 14 scl fig.39-(a) the case of 14 dummy clock + start + start+ command input normal command normal command dummy clock14 start2 * start command from start input. start9 fig.39-(c) start 9 + command input scl 1 2 3 8 9 7 sda sda normal command normal command
technical note 12/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to canc el write cycle and so forth, pay attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don't care. set the setup time to rise of d0 taken 100ns or more. the area from the rise of scl to take in d0 to the end of internal automatic write (twr) is cancel valid area. and, when it is set wp='h' during twr, write is ended forcibly, data of address under access is not guaran teed, therefore, wr ite it once again.(refer to fig.41.) afte r execution of forced end by wp standby status gets in, so there is no need to wait for twr (5ms at maximum). command cancel by start condition and stop condition during command input, by continuously inputting start condit ion and stop condition, command can be cancelled. (refer to fig. 42.) however, in ack output area and during data read, sda bus may output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during ra ndom read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, theref ore, it is not possible to carry out current read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. data not guaranteed fig.41 wp valid timing fig.42 case of cancel by start, stop condition during slave address input scl sda 1 1 0 0 start condition stop condition ? rise of d0 taken clock scl d0 ack enlarged view scl sda enlarged view ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area write forced end data is not written. slave address d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address
technical note 13/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs betw een the pull up resistance rpu a nd the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sd a terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by following relations. (1) sda rise time to be determined by the capacity (cbu s) of bus line of rpu and sda shoulder be tr or below. and ac timing should be satisfied even when sda rise time is late. (2) the bus electric potential a to be determined by rpu and rs the mo ment when eeprom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1vcc. (v cc v ol )r s +v ol +0.1v cc Q v il r pu +r s r s Q v il v ol 0.1v cc r pu 1.1v cc v il example) when v cc =3v, v il =0.3v cc, v ol =0.4v, r pu =10k ? , from(2), r s Q 0.33 0.4 0.13 1010 3 1.13 0.33 Q 0.835 k ? maximum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. v cc Q i r s r s R v cc i example when v cc =3v, i=10ma r s R 3 1010 -3 microcontroller r s eeprom fig.44 input/output collision timing a c k 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda fig.45 i/o circuit diagram microcontroller eeprom 'l' output r s r pu =10 'h' output over current fig.46 i/o circuit diagram fig.43 i/o circuit diagram r pu=10 microcontroller r s eeprom i ol a bus line capacity cbus v ol v cc v il
technical note 14/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. i 2 c bus input / output circuit input (a0, a1, a2, scl, sda) input/output (sda) notes on power on at power on, in ic internal circuit and set, vcc rises through unstable low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent this, functions of po r circuit and lvcc circuit are equipped. to assure the action, observe the following condition at power on. 1. set sda = 'h' and scl ='l' or 'h' 2. start power source so as to satisfy the recommended conditions of tr, toff, and vbot for operating por circuit. recommended conditions of t r , t off , vbot t r t off vbot 10ms or below 10ms or higher 0.3v or below 100ms or below 10ms or higher 0.2v or below 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above conditions 1 cann ot be observed. when sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(p26). c) in the case when the above conditions 1 and 2 cannot be observed. carry out a), and then carry out b). fig.47 input pin circuit diagram fig.48 input /output pin circuit diagram fig.49 rise waveform diagram tlow tsu:dat tdh after vcc becomes stable scl v cc sda tsu:dat after vcc becomes stable fig.50 when scl='h' and sda='l' fig.51 when scl='h' and sda='l' toff tr vbot 0 v cc
technical note 15/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and prevents wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. v cc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfunc tion may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1f) between ic vcc and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. notes for use (1) described numeric values and data are design repr esentative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendabl e, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluct uations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperature exceeding the absolute ma ximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that eac h terminal voltage is lower than that of gnd terminal. (5) terminal design in consideration of permissible loss in actual use cond ition, carry out heat design with sufficient margin. (6) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay su fficient attention to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause ma lfunction, therefore, eval uate design sufficiently.
technical note 16/16 bu9897gul-w www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. ordering part number b u 9 8 9 7 g u l - w e 2 part no. part no. package gul : vcsp50l2 w-cell packaging and forming specification e2: embossed tape and reel (unit : mm) vcsp50l2 (bu9897gul-w) 2.440.05 p=0.5 2 1.990.05 s 0.06 s 0.55max 0.10.05 b a 0.05 11- 0.250.05 b c a 34 0.470.05 2 1 p=0.5 3 a 0.4950.05 b 1pin mark ( 0.15)index post ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs e2 () direction of feed reel 1pin
r1120 a www.rohm.com ? 2011 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the produc ts. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redundancy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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